1. Field
The embodiments discussed herein relate to a semiconductor memory.
2. Description of Related Art
A semiconductor memory, such as a flash memory, may store data logic according to a threshold voltage of a memory transistor within a memory cell. The threshold voltage of the memory transistor varies depending on an amount of charges stored in a floating gate. When data is programmed into a memory cell that is in an erased state, the control gate of the memory transistor is set to a high level in order to generate a hot electron in a channel region of the memory cell transistor. The threshold voltage of the memory transistor is high because the hot electron is injected into the floating gate of the memory transistor.
Related art is disclosed in Japanese Laid-open Patent Publication No. H5-314783, Japanese Laid-open Patent Publication No. 2002-25280, Japanese Laid-open Patent Publication No. 2002-109891, or the like.